Study and design of silicon carbide power MOSFETs for low voltage applications

Advances in Silicon Carbide (SiC) crystal growth especially the development of chemical vapour deposition (CVD) have encouraged the fabrication of high-quality SiC. Nowadays, in the market are available wafers of quality similar to Silicon, and although the production costs are still high, they are continuously decreasing. This slow decrease in prices has aroused greater interest in SiC devices. Thus all the major worldwide manufacturers of electronic components faithful to the undisputed Silicon, have started to investing more resources to improve the production technologies of SiC devices. Moreover, new wafer processing systems have developed for improving the wafers production yield and of final quality, while reducing costs. Other developments have been achieved about post-treatment process for the wafer, indeed, nowadays the produced SiC wafers present a reduced impurity distribution that can be responsible for the formation of defects and traps. Impurities in semiconductors play an important role to modify their physical properties. The doping of a semiconductor introduces shallow defect levels to increase the conductivity. Impurities, especially transition metals, generate defect-levels deep inside the SiC bandgap, which are able to trap charge carriers and thus reduce the lifetime of charge carriers. Thanks to this recent progress in SiC-technology, power devices are now commercially available from worldwide manufacturers such as Infineon, Cree, and GeneSiC. SiC guarantee excellent devices for power applications, for example, faster-switching speed compared to Silicon devices, which can lead to superior converters performances because converters can operate at higher switching frequencies with reduced switching losses. SiC power MOSFETs are available only for above 600 V. The aim of the first part of my research is the prediction of the electric characteristics of a "novel" 4H-SiC MOSFET, tailored for power optimizers used in photovoltaic modules for low voltage category of DC-DC converters, therefore characterized by a breakdown voltage BVDS of 150 V, and currents of the order of 10 A. This study is based on numerical simulations. The obtained results show that the static characteristics would be comparable to those of Silicon MOSFETs rated for a comparable BVDS, with an ON-state resistance RON in the order of 100 kΩ×µm2. But, SiC MOSFETs show advantageous results in terms of dynamic characteristics, and in particular in terms of switching times. BVDS and RON are inversely related to each other; therefore, the RON optimization must be obtained without affecting the fixed BVDS value. Power MOSFET optimization could be pursued in different ways. Recent scientific research has proposed new cells design, such as the super-junction and lateral trench gate, both introduced to reduce mainly the RON of power MOSFETs. This problem was also addressed in this thesis. Thus, after having dimensioned the MOSFET cell for the set breakdown voltage value, the channel length has been optimized and next to the channel resistance which is a heavy component of ON-state resistance. The second part of this dissertation was carried out to detail the relative weight of interface defects and traps in a 4H-SiC MOSFET. The experimental results confirmed the theoretical ones, in fact, numerical simulations have confirmed that these can affect (in variable measure depending on the ultimate SiC-wafer quality and by other extra chemical post-processes) deeply on the MOSFET's channel, increasing its resistance. As expected, at high power, degradation processes are mainly related to impact-ionization and of hot-carriers. That of hot-carriers is a phenomenon strictly correlated to the defect and trap distributions inside the bulk semiconductor and at the interface with the gate oxide. Accurate physical models for defects and traps distributions have been studied and applied to the designed MOSFET. The role of an explicit defects state concentration at the SiC/SiO2 interface in determining the RON value of a 4H-SiC power MOSFET has been investigated. Numerical simulations have been performed and produced results have shown, for different temperatures, the traps distribution impact on the electrical characteristics. The percentage variation of RON was about 40% for low gate voltages at room temperature. More complex has been the scenario in which were considered the conjoint contributions of defect and trap distributions inside the designed structure. First of all, the conjoint behaviour of traps and defects depends mainly on their relative concentrations and where they are located inside the structure. Moreover, it is important to consider the depth where these distributions have been allocated. In this context, also temperature plays an important role; in fact, it has a strong influence not only on the physical parameters of the device but even on the defects and traps distributions. From a theoretical point of view, we can affirm that the impact of defects and traps on the physical and electrical properties of the device could be represented as a multi-parametric function with many degrees of freedom.