In this paper we investigate the optimized design of a short channel gate-all-around-junctionless (GAAJ) metal-oxide-semiconductor field-effect-transistor (MOSFET), including the source-drain extensions, by means of genetic algorithm solutions applied to a compact current-voltage analytical model. In fact, due to the complex device structure, it seems useful to exploit a metaheuristic-based approach to search the optimal combination of the fundamental geometrical and physical parameters that lead to an improved performance. Through this analysis, different parameter constraints are imposed for the calculation of specific objective functions. In particular, for a fixed gate-drain bias level, the task pursues the maximization of the drain current and cut-off frequency while limiting the short channel (SC) effects. The MOSFET series resistance is also evaluated in the transition region of the Id – Vgs characteristics which appear, however, strongly affected by SC effects. The accuracy of the model is verified by comparison with experimental data reported in literature.
Current-voltage analytical model and multiobjective optimization of design of a short channel gate-all-around-junctionless MOSFET / Pezzimenti, F.; Bencherif, H.; Yousfi, A.; Dehimi, L.. - In: SOLID-STATE ELECTRONICS. - ISSN 0038-1101. - 161:107642(2019), pp. 1-6. [10.1016/j.sse.2019.107642]
Current-voltage analytical model and multiobjective optimization of design of a short channel gate-all-around-junctionless MOSFET
F. PEZZIMENTI
Membro del Collaboration Group
;
2019-01-01
Abstract
In this paper we investigate the optimized design of a short channel gate-all-around-junctionless (GAAJ) metal-oxide-semiconductor field-effect-transistor (MOSFET), including the source-drain extensions, by means of genetic algorithm solutions applied to a compact current-voltage analytical model. In fact, due to the complex device structure, it seems useful to exploit a metaheuristic-based approach to search the optimal combination of the fundamental geometrical and physical parameters that lead to an improved performance. Through this analysis, different parameter constraints are imposed for the calculation of specific objective functions. In particular, for a fixed gate-drain bias level, the task pursues the maximization of the drain current and cut-off frequency while limiting the short channel (SC) effects. The MOSFET series resistance is also evaluated in the transition region of the Id – Vgs characteristics which appear, however, strongly affected by SC effects. The accuracy of the model is verified by comparison with experimental data reported in literature.File | Dimensione | Formato | |
---|---|---|---|
Pezzimenti_2019_SSE_Current_editor.pdf
non disponibili
Tipologia:
Versione Editoriale (PDF)
Licenza:
Tutti i diritti riservati (All rights reserved)
Dimensione
985.44 kB
Formato
Adobe PDF
|
985.44 kB | Adobe PDF | Visualizza/Apri Richiedi una copia |
Pezzimenti_2019_SSE_Current_post.pdf
Open Access dal 25/08/2021
Tipologia:
Documento in Post-print
Licenza:
Creative commons
Dimensione
642.64 kB
Formato
Adobe PDF
|
642.64 kB | Adobe PDF | Visualizza/Apri |
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.