Analysis of 4H-SiC MOSFET with distinct high-k/4H-SiC interfaces under high temperature and carrier-trapping conditions

In this work, the reliability of different oxide/4H-SiC interfaces under high temperature and carrier-trapping conditions are investigated carefully. In more detail, the carrier-trapping and temperature effects are considered in the electrical characterization of a low breakdown 4H-SiC-based MOSFET by using in turn SiO2, Si3N4, AlN, Al2O3, Y2O3 and HfO2 as gate dielectric. A gate oxide with a high relative permittivity notably improves the transistor performance. In addition, HfO2 assures the MOSFET best immunity behaviors. The obtained results are explained in terms of the carrier channel mobility, device on-state resistance, and oxide electric field. By using HfO2, however, an increased gate leakage current is calculated. This drawback is overcome by inserting a thin interfacial layer (2 nm-thick) in the HfO2/4H-SiC MOS structure. In particular, two alternative gate stacked dielectrics, involving either SiO2 or Al2O3, have proven their effectiveness in preserving the transistor on-state figures of merit while limiting the gate leakage current in the whole explored gate voltage range. To support the prediction capabilities of the presented modeling analysis, the simulations results are compared with experimental data from literature resulting in a good agreement. Low power MOSFETs are used in several applications for which reliability and durability are as critical as performance. For example, referring to power optimizers for photovoltaic (PV) modules, which fall under the low-load and low-voltage category of DC–DC converters, these devices significantly increase the energy generated by each single PV module operating under harsh conditions and stressing environments. In addition, they have to ensure high reliability over the long term of operation.